The V1 platform comes with a wider and deeper architecture that supports Scalable Vector Extensions (SVE), a type of SIMD instruction.

In contrast, Arm designed the Neoverse V1 'Zeus' platform specifically to introduce a new performance tier as it looks to more fully penetrate HPC and machine learning (ML) applications. The next-gen Neoverse N2 platform preserves that scalability across a spate of usages. Both chips utilize Arm's new CMN-700 mesh that enables either single-die or multi-chip solutions, offering customers plenty of options, particularly when deployed with accelerators.Īrm's existing Neoverse N1 platform scales from the cloud to the edge, encompassing everything from high-end servers to power-constrained edge devices. Arm says the N2 core will take the uncontested lead over an SMT thread on competing chips and offers superior performance-per-watt.Īdditionally, the company says that the Neoverse V1 core will offer the same performance as competing cores, marking the first time the company has achieved parity with two threads running on an SMT-equipped core. Arm chalks much of this design's success up to the Coherent Mesh Network 600 (CMN-600) that enables linear performance scaling as core counts increase.Īrm has revised both its core architecture and the mesh for the new Neoverse V1 and N2 platforms that we'll cover today. Now they support up to 192 cores and 350W TDPs. Additionally, Arm says that, given N1's energy efficiency, one N1 core can replace three x86 threads but use the same amount of power, providing an overall 40% better price-vs-performance ratio.

Arm Neoverse Platform RoadmapĪrm's server ambitions took flight with the A-72 in 2015, which was equivalent to the performance and performance-per-watt of a traditional thread on a standard competing server architecture.Īrm says its current-gen Neoverse N1 cores, which powers AWS Graviton 2 chips and Ampere's Altra, equals or exceeds a 'traditional' (read: x86) SMT thread. Let's start with the Arm Neoverse roadmap and objectives, then dive into the details of the new chip IP. Especially considering the full-featured connectivity options available for both single- and multi-die designs. If Arm's performance projections pan out, the Neoverse V1 and N2 platforms could provide the company with a much faster rate of adoption in multiple applications spanning the data center to the edge, thus putting even more pressure on industry x86 stalwarts Intel and AMD.

This new mesh design serves as the backbone for the next generation of Arm processors based on both single-die and multi-chip designs. Additionally, the company says that its Neoverse N2 platform, its first IP to support newly-announced Arm v9 extensions like SVE2 and Memory Tagging, delivers up to 40% more performance in diverse workloads.Īdditionally, the company shared further details about its Neoverse Coherent Mesh Network (CMN-700) that will tie together the latest V1 and N2 designs with intelligent high-bandwidth low-latency interfaces to other platform additives, such as DDR, HBM, and various accelerator technologies, using a combination of industry-standard protocols, like CCIX, CXL, and PCIe. The Neoverse V1 platform is the first Arm core to support Scalable Vector Extensions (SVE), bringing up to 50% more performance for HPC and ML workloads. Instead, we were given a deep dive look at the technology roadmap that Nvidia CEO Jensen Huang says makes the company such an enticing target.Īrm claims its new, more focused Neoverse platforms come with impressive performance and efficiency gains. Naturally, all of this becomes much more interesting given Nvidia's pending $40 billion Arm acquisition, but the company didn't share further details during our briefings.

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